Thursday, July 13, 2006

A bit of defense for SOI

I have received intelligent criticism about my enthusiasm for AMD doing the extra expenses it takes to include SOI in their silicon manufacturing, to which I gave a reply, but a new article allowed me to go deeper into the subject:

In an interview, "Turn Down the Heat ... Please" which I obtained thanks to an article in "The Register", "IBM: Cell-like CPU yields 10-20 per cent", Ed Sperling asked Tom Reeves, VP of semiconductor and technology services at IBM, what would be the next big thing in chip technology, and Mr. Reeves answered:

Through the ’70s and early ’80s, bipolars went up to 100 watts. We had water-cooling systems, but you needed something new. Then we started with CMOS, [...] Now, 20 years later, we’ve got 100 to 120 watt chips again. Power is everything. The efforts we’re taking to get leakage power down for cell phones or a base station or a Cisco switch are enormous. If you look at a chip in a base station or a switch, they’re 40 watts, and there are a lot of them. The total wattage gets up to 5,000 or 10,000 [!!]. So the major focus now is not on Moore’s Law [!!] and how you get the next density step. We’ll get that. How you get the next performance step is harder work than it’s been, too. But the most important issue is how you manage power. Leakage power at the most advanced lithography is very challenging. And with active power, can you cool the gain? College kids were hanging some gaming systems out their dorm windows to cool them down.
Silicon on Insulator may not help at all to overclock a µ-processor, which is a nice feature that the gaming market appreciates (the materials used for SOI are good heat insulators as well, thus they obstruct the efforts to extract the extra heat that the overclocker forces the processor to generate over volting and over clocking it), but still, it helps with the very important leakage.

The simplistic explanation is this: The transistor behaves a bit as a capacitor, to switch, it needs to get rid of the charge it accumulated. The lower the charge, the lower the energy leakage associated with switching, and the lower the capacitance the lower the charge. SOI helps precisely about lowering the capacitance. According to the wikipedia, SOI helps 30% with the transistor leakage, and 15% with switching speed (of course, it takes less time to get rid of a lower charge at the same current level (because the voltage is the same and the resistance too)).

We shouldn't take Mr. Reeves opinion as that of an interested party, what he points out is perfectly clear and true. Power, it is Power the issue of these times. The usage of the more expensive SOI technology, and harder to market slow clock speeds, is a sign of a pervasive attitude at AMD: They focus on solving the real technology issues. Just like I said in "65nm Is Just Intel Marketing", Intel doesn't bother, at Intel, the basic question is this: "Can we market technology defficient products?", if the answer is positive, Intel won't do power efficient processors, nor good architectural features. Rather, what Intel attempts is to sell products with marketing-amiable catchphrases such as "Gigahertz" (remember that Pentium 4s only cared about the clock speed, although they couldn't do as much real processing as an Athlon at half the speed, while consuming a lot of power!), "Hyperthreading", which was so poorly implemented that rather than providing a huge speed boost, as it should, provides a decline. 65nm products that so far are not even at par with current AMD products. "Dual Cores" that are really multi chip packages, and it now spins the weaknesses of not having neither the integrated memory controller nor a processor interconnect as a great advantage that "allows" to put gigantic caches and a stupid memory architecture flexibility, because it's something you can't do much with.

It is the same approach everywhere. For server processors: "Can we market processors for servers although they can't scale past the four cores because they don't have any processor interconnect?", "Can we fool our customers with Netbursts while they want to buy Woodcrests?", yeah, let's name the Dempseys Xeon 5000 series and the Woodcrests Xeon 5100. A great question is how long can Intel succeed with lies. It has taken decades to merely crack Intel's monopoly, which was constructed with lies and deception. How long would the monopoly remain given that Intel insists in blatant lies?

There is no wonder that at Intel they don't expend the extra doing SOI, they prefer to expend expend extra in marketing to convince people that SOI is an unnecessary expense.


jackall said...

"Through the ’70s and early ’80s, bipolars went up to 100 watts. We had water-cooling systems"
O_o ? Chips went up to 100W in the 70's. Damn, I didn't know that. Its amazing that we got back down to chips with only heat sinks in the Late 80's and 90's? I guess its time to start googling and "WIKI P'ing" (did I just coin that?)

I love AMD. They since the Athlon and even the K6-2 have been the ones leading the industry in innovation and implementation.
Lets hope that intels current restructuring will not only include making the company leaner and more profitable but also involve a major change in philosophy.

Eddie said...

AMD also bought NexGen, which probably was the most innovative µprocessor company the world has seen so far.

That was the foundation for everything good AMD is doing today, and also the origin of the excellent CTO Fred Weber (who unfortunately departed AMD to become an venture capitalist)

Anonymous said...

Please stay away from process technology discussions, as you have no idea about SOI and have shown a clear lack of Si process technology in previous posts.

Wikipedia is NOT a technical data source and their info on SOI is lifted almost verbatim from another website of a company that uses SOI (and therefore has a vested interest in promoting its benefit).

To bring this around to a technical discussion - how is Intel's Ion/Ioff ratio on 65nm technology better than AMD's? (especially if Intel is handicapped by not using SOI). Do you even know what Ion/Ioff ratio is and why it is a significant benchmark?

There are alternate means of preventing the leakage that SOI prevents (junction leakage for those of you who care) and they are often cheaper than the significant added cost of a 300mm SOI wafer. While I guess it can be cool to go with an expensive "elegant" solution if you could accomplish the same thing in a simpler and more cost effective way why not?

Are Intel's 65nm Core2 products on par with AMD now? Do you suppose perfomance/power issues with netburst (which uses same 65nm technology) may have been due to architecture design and not process technology?!?!?

You keep assigning leakage to a CPU's power consumption. It is only one component: design, active power from clock speed, sleep states, supply voltage, transistor threshold voltage, # of transistors, etc...

Intel's off state current (Ioff) for a given active current (Ion) without SOI is superior to AMD's 65nm Ion/Ioff with SOI (published via either IEEE or IEDM which unlike wikipedia are actual technical bodies).

And I don't believe Intel is marketing Core2 based on GHz. (Is it not AMD who is starting to crank up GHz with FX62/64/66 now?)

Anonymous said...

"SOI helps precisely about lowering the capacitance."

I'm stunned, this is actually correct - perhaps you can inform us of how SOI-based solution is able to do this?

Eddie said...

No, I don't know what is the ratio lon/loff. I don't claim to be an expert in this field, of silicon processing.

Does that invalidates me from mentioning an opinion? I carefully mention the sources and explain the best possible why I reached a conclusion. That doesn't prevent me from being wrong, but it certainly helps.

Look, if you don't like what is available in the wikipedia, you can do a lot of things before coming here to bash me for quoting: You can modify yourself the article on SOI, you can point out links to where SOI is treated as just an expensive way to deal with one problem, you can even explain yourself about other ways to reduce the power consumption on µprocessors.

But what you fail to understand is that the burden of the proof is yours, not mine; so far, you just claim that I am so ignorant that I should keep quiet, well, come on, be up to your standards and write.

Explain what is the lon/loff, I guess it is the ratio of power consumed in "On" to "Off", or something like that, it makes sense to measure that. Now, how could I know that Intel as a better ratio than AMD?

I chose to quote the wikipedia because its explanation makes sense. If it is a marketing promotional material, it still makes sense. And I provide the exact link, so that anybody could check it for himself. Now you come and make a lot of claims, well, substantiate them.

All I know is that the problem of leakage grows exponentially with the density, and that the expensive layer of insulator may be just what is needed. And that SOI has added beneficial side effects, such as Z-RAM.

Eddie said...

By the way, "Anonymous" critic: You should leave a handle to refer to you. I am not asking for your name, just something to know that it is the same person who is talking.

And, please, don't criticize my posts misunderstanding them: You said that "I don't believe Intel is marketing Core2 based on GHz", neither I do. I was just pointing out the fact that when Intel could fool the market, it sold meaningless gigahertz. Now, things are much tougher, because the market learned to respect AMD processors with clocks **much** lower, so much, that Intel had to endure to lose face and acknowledge total defeat.

About the Core µarch. There isn't any product in the market yet. Woodcrest was paper launched some weeks ago, Conroe hasn't even been paper launched yet. As soon as any store has them in stock and I have only to wait for the delivery (not for the store to first acquire them), I will not say that AMD's products are the undisputed leaders in performance.

Anonymous said...

"But what you fail to understand is that the burden of the proof is yours, not mine; so far, you just claim that I am so ignorant that I should keep quiet, well, come on, be up to your standards and write."

Ion/Ioff is in many technical publications - I put this in my response. Here is a link should you need one:

One other word of note - IBM's PMOS reported performance is actually slightly inflated because they are reporting it at 200nA/Um as opposed to 100nA/um with the Intel #'s. (this is not an intentional deception, they are just reporting at a different Ioff)


Typically when one makes a statement, you support it not tell others to "prove that I'm wrong."

AMD yields are 30% - prove that I'm wrong...I will provide no links to support this, but it is a fact. (I assume your response to this, rightfully, would be - you are full of crap).

What I'm stating is that you clearly have demonstrated limited knowledge in Si processing and yet you continue to publish info as if you are an expert in this area when you have very little idea of how SOI actually impacts transistor operation and physics. Then without having this knowledge you go on to say Intel's 65nm approach is just marketing when any reputable scientific benchmarking will tell you that's not the case (Ion/Ioff being one of numerous ones).

Other ways to reduce power:
1) Architecture - evidence being Netburst vs Core2 on same technology node)
2) Thicker electrical gate oxide thicknesses. This however degrades performance if you just thicken SiO2 - Intel did this on their "1265" process which is a variation of their 65nm process for low power/lower performance applications. This can also be done by swithcing to high K oxides without the performance hit (something the industry has been working/researching for a while now).
3) Increase transistor size - this is something AMD is doing on their low power athlon (not sure what they call this) - the proof here being the number of transistor went down while die size went up for these products vs their original higher power versions.
4) You can adapt the turn on voltage ("Vt") for portion of the circuits that are not speed critical. Both Intel and AMD do this (Intel uses a dual Vt, I beleieve AMD now uses 3 Vt's on a single chip.)

Let me know if you'd like to understand other ways to reduce power on chips.

Anonymous said...

Sorry two last things of what I think is wrong with your blog:

"I chose to quote the wikipedia because its explanation makes sense. If it is a marketing promotional material, it still makes sense. And I provide the exact link, so that anybody could check it for himself."

Because a source of information "makes sense" doesn't make it accurate. You then leave it up to the reader to determine the accuracy of the source as you do not have the technical background to do this for yourself. While I know this is not journalism, that in my opinion, is irresponsible ("Here is a link, I have no idea whether is is accuracte or not but I will quote it because it makes sense").

"There is no wonder that at Intel they don't expend the extra doing SOI, they prefer to expend expend extra in marketing to convince people that SOI is an unnecessary expense."

This is a nice conclusion to support your AMD bias but unless you worked at Intel how could you possibly know and/or conclude why Intel is not doing SOI? Based on their published 65nm performance, is it possible they have determined scientifcally that there are alternate ways to do the same thing?