Tuesday, December 04, 2007

More terrible news about Phenom and K10

[ UPDATED 12/5/12:04 CST ]

More lies come from AMD, and the performance of their products is significantly worse than in early reviews:

Giant in a comment at Roborat64's blog mentioned something important:

TechReport reports that their original Phenom benchmarks were done incorrectly, that the actual performance is worse than reported, you may find it at the penultimate paragraph:

We don't yet have a BIOS with the [ L3 Cache ] workaround to test, but we've already discovered that our Phenom review overstates the performance of the 2.3GHz Phenom. We tested at a 2.3GHz core clock with a 2.0GHz north bridge clock, because AMD told us those speeds were representative of the Phenom 9600. Our production samples of the Phenom 9500 and 9600, however, have north bridge clocks of 1.8GHz. Because the L3 cache runs at the speed of the north bridge, this clock plays a noteworthy role in overall Phenom performance. We've already confirmed lower scores in some benchmarks.
It is reasonable to assume that other sites may have done the same mistake, so, the already bad Phenom reviews are actually worse...

But that is not the important thing I want to talk about, it happens that "techreport" almost confirms that AMD lied regarding the reason why it couldn't launch Phenoms at 2.4 GHz and faster, that supposedly only affected the 2.4 GHz and over; it turns out that the problem is pervasive to all the current K10 incarnations, from Barcelona to Phenom, this is what Scott Wasson at "techreport" said about this subject yesterday: "Apparently contradicting prior AMD statements on the matter, [Michael Saucier, Desktop product Marketing Manager at AMD,] flatly denied any relationship between the TLB erratum and chip clock frequencies".

Not just this, but since the bug first showed up at Barcelona (that eventually led to a drastic cut of supply of defective product, only to those who have usage patterns such as supercomping not likely to trip the bug as opposed to virtualization workloads that are likely to trip it), AMD should have expected Phenom to have the same problem, but instead of postponing the launching of Phenom, the company went ahead and launched a defective series of processors.

Scott Wason connects the dots and mentions this:
[T]he presence of the TLB erratum may explain the odd behavior of AMD's PR team during the lead-up to the Phenom launch, as I described in my recent blog post. The decision to use 2.6GHz parts and to require the press to test in a controlled environment makes more sense in this context
It turns out that the BIOS patch that prevents the problem, that also includes microcode updates, turns off functionality of the L3 cache with an official impact of 10% of performance, or 20% according to early independent reviews. Let's use the official 10%, if we simply reduce clock speeds by 10%, the products AMD launched were not faster than 2.1 GHz... But this patch is not available today for the majority of 790FX platforms!

There is also the rumors that AMD will launch triple cores without L3 cache. This would confirm my appreciation that the L3 cache provides dubious performance advantages, but as you may see, it is another point of failure in the development of the architecture.

In summary:
  1. K10 is buggy, in accordance to the predictions regarding the "triple challenge" of developing a new architecture on immature process and managing the complexities of single die quadcores [ I wrote an old article about why I expected that the sheer complexity of "Core" was going to be too much for Intel, but it happened that it was the "triple challenge" complexity what is too much for AMD, just like "Intel's 65nm is Marketing" applies much better to AMD ].
  2. AMD lied about why it couldn't launch Phenoms at 2.4 GHz and over (2.6 GHz were promised a long time ago), this is more of the same bullshit as saying that the L2 latencies in Brisbane were higher supposedly to allow for larger caches in the future (the caches didn't increase in the 12 months after the launch of Brisbane, by the way).
  3. Knowingly, AMD launched defective products
  4. The performance reviews of Phenoms must be revised downward significantly, once the actual bugfixes are availabe, which make take a while!
  5. AMD influenced reviewers to make a mistake (to set the external clock to 2.0 GHz) that would show Phenom in a more positive light
  6. AMD tried to hide the problem at the launching of Spider.
I felt the need to update this post because I didn't speak about the implications:
Traditionally this is the most important season for businesses like AMD, but the products in the market may even be recalled and it will take some time, in the order of months, for AMD to be able to correct the problems, we are talking of late Q1, the worst business season...

I just wrote in "A-TItanic" that Dr. Ruiz several times said that K10 will not affect the finances of the company this year, that early production was for "design wins", but if something is very evident is that even bug-free K10 stink, so who is going to wait more months to buy such mediocre products?, or what motherboard designer is going to bother with K10 features like HyperTransport 3 and such?, what is AMD going to do with the K10 products it already manufactured? What about Penryn? This is all too much to ask to the venerable K8 architecture.

After all, it seems that K10 will affect the finances of AMD this year: very negatively.


Anonymous said...

So are you actually saying some of your early predictions about Intel & core 2 were a little off?

I'm not dissing, in 2006 it was very easy to see Intel as not being capable of getting anything superior to the K8 out any time soon. I just think it's unusual & refreshing to see someone admit to being wrong about something. (Sharikou will never get this).

Eddie said...

Hello there.

I was completely wrong about the complexity of the Core µarchitecure and about Intel's 65nm, but I still link to the old articles because they not just contain predictions, they contain reasoning that is pertinent today.

There are several other articles where I explain why I began with one opinion and upon further data got to the opposite.

I still don't quite understand how Intel has gotten so far with an apparently exhausted µarchitecture; regarding the 65nm it turns out that for some reason, perhaps related to SOI, AMD had a much worse problem of diminishing returns than Intel, it makes me wonder about the 45nm transition without the great two advances Intel made

Anonymous said...

Links to description of the affected errata plus linux kernel patch are given in this post, courtesy of Andi Kleen from SuSe.