Thursday, October 12, 2006

A new µarchitecture every two years... ¿Can you believe that?

Well, Intel announced that, beginning with Core2, they will unleash unto the world a new µarchitecture every two years. ¿Can they really do that? ¿Why are they doing that? ¿Will it fly with the customers? While only time will tell, I gazed into my LCD ball, and tried to see the future, and here are my predictions...

Lets clarify a little what is their plan. Each new µarchitecture will be produced with a target feature size in mind. When the new one debuts, on a new feature size, the old one gets a "Mask Shrink", and so on. To put it into perspective, Core2 was designed with a target Fab Process of 65nm. When Core3 debuts in around two years time, it will debut in 42nm and Core2 will be Mask shrinked as well. When Core4 debuts, it will debut with an even smaller feature, Core2 will be slowly discontinued, and Core3 will be mask shrinked to this new feature, and so on until Intel changes strategy again, or they go Bankrupt in 8 quarters like Sharikou Ph.D. Boy Genius is Predicting.

* First comes the question about if they can do it. Well, to do this you need three things: Money (with which you can buy the other two), People, and Fabs.

The first thing is the money. Well, if anyone around here doubts that Intel has bucket loads of that, he is in absolute denial. But, just in case, lets analyze the money that counts the most for this: the R&D budget!

IEEE Spectrum publishes each year a survey of the Top100 firms in R&D spending around the world. There is everything there, Car makers, Pharma, telecoms, Chip making, Electronics, the works! I told you in a previous post (the Coin has Three Sides) to go check it out. Since most likely none of you people did it, here is the resume:

(Position/$) 2.002 2.003 2.004
Intel 11 / $4034 Million 15 / $4360 Million 13 / $ 4778 Million
AMD 83 / $816 Million 89 / $852 Million 89 / $935 Million

And here are the links...

Needless to say, there is R&D budget, even if you consider (as many of you would) that not all that money goes into X86. Just think that if Intel decided to spend double that of AMD in X86 alone, that would be just 39% of its R&D budget... Man, the money is there.

As per the Fab capacity, think for a minute of "CopyExactly! "®©. Forget for a second what Sharikou and Chicagrafo have been telling you and free your mind... That set of "Best Practices" was made in a world were Intel had more than 80% marketshare of all the µprocessors in the world. The idea was not to get an elegant solution, or kick-ass technology, or to be nimble and flexible to better react to changing demand from customers, or to be able to run test wafers alongside production ones. It was made to ramp up production of a new model FAST. Intel has lots of Fabs, many of them CopyExactly! ready, so yes, once the microprocessor is designed, it will be produced, and quick.

Finally, well, no doubt about they have the people. Just like AMD has a great deal of good people (what Sharikou dubbed and Chicagrafo picked up as the "Grand Masters") so does Intel. If anyone wants to do head count, is more than welcome. But since we also can not read their full CVs, well, there is not much to say about it.

A more interesting question is, how you organize the people to accomplish this? Well, as it has been said before, you just pipeline the design process. Each two years or so, a new design team starts designing the next microprocessor. Since the design process can last anything from four to six years, you will have several teams working in different µArchitectures, with different feature size targets at the same time.

* ¿Why are they doing that?

To answer this questions, two ideas come to mind, and I am sure the audience can come with more.

1.) Imagine that you take a commuter train home. The trip lasts 60min, and you get one train every 40 minutes. If you arrive to the platform just to see the door of your train closing, it will take you 100min to get home (40min waiting for the train, and 60min more traveling). Now imagine that now you get a train every 20min. In the case just described, it takes you now just 80min to get home. Now, imagine that, just after initiating a new design cycle, Intel just discovers that AMD did something really revolutionary they never thought off (or alternatively, that Intel shoot itself in the foot), well, with this new scheme of things, they have to wait less to fix the blunder and get the fix to the customers.

2.) The other reason is to give customers compelling reasons to wait. If a customer hears that AMD will give them a 20% speed bump now, but your Intel salesman comes and says: "You know, instead of doing a costly forklift upgrade (read the quadcore part of my three sides of the coin piece to see why a forklift upgrade is costly) to your 500 blades and your 2000 machine cluster to get a 20% speed increase, wait for our new architecture that is just around the corner, get a 40% (or more) speed upgrade and avoid the (very costly) forklift upgrade "

* ¿Will it fly with the customers?

Well, the economics seems right. The other thing they need to do is to convince the customers that, even though the µArchitecture is changing, the chips will be compatible with the infrastructure. That is to say, you will be able to put the new chips in the mobos of the old ones, either in the same (CSI) sockets, using a socket adapter, or by having spare (¿remember overdrive?) sockets in the mobo. Please notice that the important thing here is to convince the customers, not your technical ability to deliver this compatibility, so, this is more a marketing issue than a technical issue... and we all know Intel marketing.

* One question I keep hearing is if this will involve evolutionary changes, or revolutionary. Well, the answer depends on your definition of revolution. Let history be your guide, and think of this timeline:

8086/8088: Baseline

80186: Evolutionary: Peripheral chips incorporated on the µProc die.

286: Revolutionary: Protected memory (among other things).

386: Revolutionary: 32 Bit mode

486: Evolutionary: Coprocessor integrated

Pentium: Revolutionary: First Superscalar X86.

And, here is where the plot thickens:

Pentium MMX: Is it revolutionary to add SIMD instructions to the X86 set? I think it is, others may not.

PPro: It is revolutionary for Intel to have a RISC core and a CISC translation, but AMD did it

before, and NextGen did it before AMD. The bus used was also revolutionary, so much so that AMD had to "borrow" DECs to remain competitive.

PII,PIII: Getting a PPro and adding more SIMD instructions to it does not seem that revolutionary.

Netburst: The Hyperthreading is revolutionary for the X86 world, but the concept is old, and the Power G5 beat Intel to it.

As you can see here guys, what will happen is that, more often than not, there will be revolutions in some parts of the µprocessor, and evolution in others... So, we will talk about a processor which is 80% evolutionary, or only 30% revolutionary. And this is the name of the game.

Thus far, I see very high level in the comments. Let's keep it like that. But bear in mind that I have other things to do (tomorrow I have a big presentation, and CV introduction marathon) so, do not expect an answer to every comment.




imnotquiteasanonymous said...

Good post! Howling and Chica, I admire you.

I also have a few comments.

First, not every new uarch attempt is successful, and they (new uarchs) seem to, at least in my view, take a very long time to develop up to the point of seeming like a good bet to take through validation and mass market manufacturing.

If you have bazillions of dollars, hordes of designers, etc., you still have to deal with the process and logistics... and you're still making a multi-year gamble that at least one of those teams has the chip that will make you a winner.

Again, I go back to Nehalem. Yes, it was just a code name and a dream... a big dream (10 GHz--heh, talented design guys, sure--but hindsight makes one ask, "what the hell were they thinking?"). And even if you discount Nehalem as a marketing ploy that no Intel chip designer ever took seriously, then one must ask the question, "if not a 10 GHz chip (as advertised), what were they working on?"

Surely, one of those things was what is now known as Core. Even so, there were all kinds of issues bringing Core to market, and all kinds of issues making an evolutionary chipset (Bensley) work with revolutionary memory (FB-DIMM), with what started as an evolutionary processor (Dempsey) that took so long to get to market that it was a 2 month shadow that nobody wanted, prior to Core hitting the market. (Sorry about the run-on sentence, but look at all the things Intel tried to pull together at once... validation and logistics were killers).

I'm not saying anything is better for AMD. K9, K10... meh. Sometimes you bet lucky (K8) and sometimes you bet unlucky (as K9 and K10 appear to be).

Those chip design teams succeed on five basic things. Enormous talent, consistent efffort, prescience (call it good judgement, lucky guesses, tomato, tomahto), money, and evangelism.

Intel has had its share of examples where they showed well on each of those 5 fronts. AMD's history on that front has been much more limited... but that's all in the past.

In my mind, companies "go evolutionary" most of the time, and revolutionary occassionaly...

...(more often then not, when the risk of not going revolutionary--and then succeeding with the revolution--clearly has severe consequences).

What that all means to me is that if AMD completely flops on execution over the next year, Intel will stop chanting "viva la revolution!" because they'll be able to rest on evolutions of Core2. It's not as if there's any other serious competition out there. Same deal with AMD, I think. Some would call that "not taking any risks with one's lead."

As it stands, I think that if AMD continues to be reasonably successful and maintains (or increases) its market share over the next few years, Intel and AMD will settle into a relatively comfortable duopoly over the next few years. Both will have too much to risk at that point to try anything revolutionary (IMO, at that point, revolutionary will read as: "stupid")

Stupid... like what Charlie D at theinquirer calls "shotgun podiatry."

Eddie said...

Howling gives us the reasons why Intel went that route.

Nevertheless, from the technical point of view:

1) Intel is inefficient with its R&D 'cos they have to do more than just focusing on good products such as stop-gap measures. Is AMD distracting R&D for MCM Quads?: No. AMD is only expending in smash after smash, in a cycle of revolution/consolidation/revolution, without "me toos". Is AMD having a dead project such as Itanium?

2) Intel can not dictate market terms anymore. It is not a monopoly any longer. Thus, Copy Exactly! leaves them in a bad position to react.

3) It doesn't matter if Intel does a µ-arch every month:
They don't have a half decent processor intercomm, with a new µ-arch. every flush of the toilet, rather than increasing the chances of closing the gap to AMD, Intel actually **dillutes** them because more teams would have to be coordinated, and there will be lesser chances to try something revolutionary, even if it is the most acute technological need of the products.

AMD is upping the ante with the leverage of ccHTT, coprocessors and integrated GPUs.

The Alexander's Macedonian Army was insignificantly small compared to the huge armies they faced, but they won because they always had the edges of superior leadership and better troops.

The new µ-arch. every flush of the toilet may very well be a shoot-the-turkey campaign for AMD, Intel, rather than gathering all of its resources to come back with a huge revolution which could wipe AMD out of the world, decided to "throw stones" at AMD every two toilet flushes.

howling2929 said...

I am sot so Anonymous:

I owed you the answer about the "many faces of Nehalem", and here it is:

Intel (and AMD and all the others) has processor roadmaps stretching far in the future. They have to gaze in their CTR or LCD balls and try to figure out 2 or 3 process generations (Think nanometers) latter what a processor will look like.

To that processor they give a code name and announce feature size and "possible" specs. So Nehalem is not a 10Ghz processor. Nehalem was "the processor whose feature size at the moment of introduction was to be 42nm" and that, at the moment of anouncement (circa 2003) was supposed to be a 10Ghz part. As we moved closer to the 42nm time horizon, we discovered that 10Ghz parts were not feasible, and thus Nehalem is now something like a 4 core Core3 part, but, look at it, it is still the processor whose debut feature size will be 42nm.

Check the documentation, and see that feature size is the only constant factor in the "multiple faces of Nehalem".


Leave the Rants aside, and think strategicaly for a moment.

I forgot to put in my article my predictions for what will be there in the next cranck of the design. One is the return of Hyperthreading, the other two, easy bets are most (I do not think all) of the memory controller inside, and finaly the famous CSI.

With CSI, hopefully for them, Intel will have a decent interconnect. That type of thing is precisely why they will do the "every two years move" to react faster to architectural threats.

And, by the way, search for Geneseo, see who is backing the initiative (aside from Intel) and think (both technicaly and from a business point of view, unless you want to leave the business and strategy part to me ;-) ) what this means for the coprocessor market that AMD is trying to spur with Torrenza. [Hint: It will not eliminate it, but it will eat the lower end of that market.]

Eddie said...

Howling, by the time Intel launches CSI AMD will be a multicoprocessor platform.

If the market for processors is mature, a business segment of low margins, etc., the GPU market is not.

AMD is developing as we speak a revolutionary technology market of coprocessors. That deserves a blog post on its own, but a quick summary:
1) GPU coprocessors
2) Physics coprocessors
3) Cryptography, Java, etc.

AMD also promises a consolidation path for coprocessors in the form of modular processors that can incorporate the coprocessors.

AMD has resounding strategic advantages to do that:
1) A high quality GPU division second only to nVidia and way above Intel
2) Partnerships with IBM, who already solved the problem of integrating sub-processors in a processor like the Cell.
3)ccHTT in fairly mature stage to test the waters with actual, real life deployments of coprocessors. Have you seen the latest announcements of supercomputers from IBM or Cray? they are mixed architecture, in which ccHTT/Opteron is the glue that holds everything toghether. And Sun is coming right after. And Raza-Alchemy is going to bring low end coprocessor opportunities.

All of this is happening, think about all the "new" architectures that Intel is going to put in the market while AMD strikes with this wave of true innovation.

Again, like I said months and months earlier, it is a situation of steam train engines versus Diesel/Electric, it is irrelevant that the greatest Steam Train Engine company of all times chose to come to market with a new design every toilet flush.

Eddie said...

Ah!, about Intel's new architecture every toilet flush: Will Intel be able to produce, let's not speak of optimal, but merely adequate product mixes?


Today Intel is producing Pentium 4s that have been demonstrated to be total dogs in the market to create himalayan-tall mountains of unsold inventories, because it simply doesn't have the production scheduling flexibility -- Copy Exactly!

Take the problem to the square power and you'll see what's the real consequence of halving the architectural introduction cycle.

Intel is losing credibility with every busted initiative. Let's see about the double dual cores in a few months.